When a clock generator in an electronic device generates a single frequency, emission of this frequency and higher harmonics increases. For this reason, use is made of a spread spectrum clock generator (SSCG) that reduces the peak of unnecessary emissions by frequency modulation and diminishes EMI (electromagnetic interference).
Operating frequencies have risen in recent years and the problem of bit-to-bit skew in parallel buses has become more conspicuous. This has led to the spread of serial interfaces that are free of bit-to-bit skew, and such interfaces have come to be employed also in personal computers in general use. For example, SATA (Serial ATA) is used as the interface standard between a hard disk and a CPU. SATA is a serial interface standard in which the first-generation communication speed is 1.5 Gbps and incorporates a spread spectrum clock (SSC) standard as an EMI countermeasure in order to be used in personal computers and the like.
In general, a PLL (phase-locked loop) using a pulse-swallow frequency divider is employed as an SSCG. However, an SSCG that employs a phase interpolator and a controller and not a pulse-swallow frequency divider and VCO (voltage-controlled oscillator) also is known in the art (see Patent Document 1).
Further, there is need for an operation in which, during the operation of an SSC (spread spectrum clock), the SSC function is turned off temporarily and then is turned on again upon elapse of a prescribed period of time. Since it is required that this operation also be changed over reversibly, it is necessary that the transition between the on and off states of the SSC function be performed smoothly. Such a function is not available in the conventional SSCG, a transient frequency change is produced at the time of changeover and an interruption in communication occurs.
Patent Document 1 filed by the present applicant discloses an example (see FIG. 4 and the third example in Patent Document 1) that is well suited to the SSC standard (degree of modulation: 0 to −5000 ppm; modulation frequency: 30 to 33 kHz) of SATA. For the details, reference should be had to Patent Document 1. A brief description will now be set forth.
In the SCCG described in Patent Document 1, as illustrated in FIG. 5, a down signal 6 is supplied to a phase interpolator 4. The frequency of occurrence of a delay Δ of a prescribed amount with respect to a clock signal that is supplied to an input terminal 1 is controlled. As illustrated in FIG. 6, a modulated clock signal is output from an output terminal 2, thereby implementing an SSCG suited to a standard referred to as “downspread”.
In Patent Document 1, the phase step of the phase interpolator 4 in FIG. 5 is assumed to be 1/64 (resolution N=64, period T0 of the input clock signal= 1/64 of 1/1.5 GHz holds) and the frequency dividing ratio of a preliminary frequency divider 21 is assumed to be 4. A conditional equation for meeting the SATA standard is as follows:1500/0.033≦2×m×p×u≦1500/0.03  (1)With regard to a count p in a p-counter 22 and a count u in an up/down counter 23, a value that satisfies this equation is assumed to be 77, and the modulation frequency is assumed to be 31.62 Hz.
The value u in the up/down counter 23 is updated whenever the p-counter 22 counts 77 times. Based upon the combination of the value in p-counter 22 and the value in up/down counter 23, a controller 24 generates the down signal 6 that retards the phase of the output clock signal of phase interpolator 4.
The number n of logical “1”s of down signal 6 within a reference number k (=m×p) of periods is successively incremented, the frequency of occurrence of phase delay Δ of the phase step 1/64 (resolution N=64) of the phase interpolator 4 is raised, and the value u in the up/down counter 23 is counted up successively from 0. When the count becomes 77, n is made 77 and the maximum modulation is applied to the clock output from the output terminal 2. The value u in up/down counter 23 is subsequently counted down and n is successively decremented, thereby changing the average frequency f in the reference number k (=m×p) of periods.
If the phase step of the phase interpolator 4 is 1/N (= 1/64) of one period T0 of the clock signal at the input terminal and the average period of the clock signal when the number of down signals 6 in the reference number k of periods is represented by T<average>, then we have k×T<average>=k×T0+(n/N)×T0 and the average frequency f<average> is
                              f                      <            average            >                          =                  k          /                      [                                          k                ×                                  T                  0                                            +                                                (                                      n                    /                    N                                    )                                ×                                  T                  0                                                      ]                                                  =                              (                          1              /                              T                0                                      )                    ×                                    (                              k                ×                N                            )                        /                          (                                                k                  ×                  N                                +                n                            )                                          
As illustrated in FIG. 7, the modulation waveform according to the above-mentioned combination is that obtained by modulation at a modulation frequency of 31.62 kHz. A single modulation period Tfm is given by 2×m×p×u×T0, and we have Tfm=31.6 us (micro second) from m=4, p=u=77, 1.5 GHz=1/T0. That is, this is a triangular wave in which the maximum modulation frequency is 1500 MHz and the minimum modulation frequency is 1494.2 MHz.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2005-4451A (Pages 5 to 9, 11 to 13, FIGS. 1, 3 and 4)
With the conventional SSCG described in Patent Document 1, however, the SSC function is implemented by the preliminary frequency divider 21, p-counter 22, up/down counter 23, controller 24 and phase interpolator 4, and the SSCG is not equipped with an SSC-function on/off changeover circuit.
Consequently, with the conventional SSCG, it is not possible to implement an operation in which, during the operation of an SSC, the SSC function is turned off temporarily and then is turned on again upon elapse of a prescribed period of time. Further, implementing a function whereby the transition between the on and off states of the SSC function is performed smoothly is a problem.